In the manufacture of integrated-circuit semiconductor device chips including device structures such as, e.g., field-effect or bipolar transistors, individual device structures are typically separated and electrically isolated by a so-called field oxide which is produced by locally oxidizing a silicon surface portion. For this purpose, localized oxidation may be effected by exposure of a wafer substrate to an oxidizing atmosphere under pressure, while device areas to be protected from oxidation are covered by a layer of a suitable masking material such as silicon nitride. Refinements of this technique include an additional thin layer of silicon oxide, known as pad oxide between the substrate and the silicon nitride layer, such inclusion being motivated in the interest of stress relief. Furthermore, in the interest of minimizing an undersirable "bird-beak" formation at the edge of the field oxide, inclusion of a third layer between the silicon oxide and the silicon nitride has been proposed, consisting of polycrystalline silicon as disclosed, e.g., in
U.S. Pat. No. 4,541,167, issued Sept. 17, 1985 to R. H. Havemann et al., and in the paper by
N. Hoshi et al., "An Improved LOCOS Technology Using Thin Oxide and Polysilicon Buffer Layers", Journal of the Electrochemical Society of Japan, Vol. 98 (1984), pp. 78-83.
Typically, after forming of the field oxide in the presence of a mask structure as described above, it is desired to strip-etch the silicon nitride and polysilicon layers of the mask structure, with phosphoric-acid wet etching being used for silicon nitride, and plasma etching for polysilicon--while the silicon substrate remains protected by the pad oxide. It has been observed, however, that such protection may fail especially in the vicinity of the field oxide, and that the substrate may undergo ruinous etching there. The invention described below is motivated by the desire to prevent such etching of the substrate in the course of stripping of silicon nitride and polysilicon.